搜索资源列表
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
DPLL
- 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
gh_timer_8254
- VHDL Source code for 8254 timer/counter
sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
altera_sdram
- SDRAM控制器的VHDL代码在FGPA中的综合与实现-SDRAM controller VHDL code FGPA and implementation of integrated
HDLC
- hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
VHDL-SPI-Module.doc
- 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmit
scrambler_17
- this parallel scrambler verilog code -this is parallel scrambler verilog code
88fifovhdl
- 88位进出缓冲器8*8位的fifo数据缓冲器的vhdl源程序 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-88 out of 8* 8-bit buffer fifo data buffer vhdl source Bianle Ge 8* 8-bit data buffer fifo vhdl source code is compiled through quartusII4.2 successful progra
a_vhdl_8253_timer_latest.tar
- 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
rom
- Rom的读取的Verilog代码，自己编写的，大家参考参考啊-Rom read the Verilog code, I have written, your information ah
I2C_Interface(VHDL)
- I2C总线接口FPGA的实现代码，全部为VHDL语言源码文件，内附设计实用说明文档。-I2C bus interface FPGA implementation of the code, all source files for the VHDL language, included the design and practical documentation.
hdlc
- hdlc 总线的vhdl 的样例代码。包含代码和说明文档。-hdlc-bus vhdl sample code. Contains code and documentation.
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
dft
- verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
wave
- 可控脉冲发生器的VHDL源代码。设计文件加载到目标器件后，按下按键开关模块的S8按键，在输出观测模块通过示波器可能观测到一个频率约为1KHZ、占空比为50 的矩形波。按下S1键或者S2键，这个矩形波的频率会发生相应的增加或者减少。按下S3键或者S4键，这个矩形波的占空比会相应的增加或减少。-Controllable pulse generator of the VHDL source code. Design documents loaded to the target device and p
lcd-code
- 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
QAM16_Souce_code
- QAM 16 源代码，用于无线通信中或者广播中的调制。-QAM 16 source code, used in wireless communication or broadcasting.